A computer system's bus conveys all the information and signals involved in the system's operation. Generally, one or more busses are used to connect a CPU (central processing unit) to a system memory and to the input/output components so that data and control signals can readily be transmitted between these different components. Expansion devices are connected to the computer system and its CPU via the bus structure. Hence, the bus structure is critical to the overall performance of the computer system. A bandwidth constrained, high latency bus architecture acts as a bottleneck which slows down the overall performance of the computer system, regardless of the performance of the expansion devices coupled to the computer system or CPU's speed and power.
Typical computer system operations often require the efficient transfer of large blocks of data. Such transfers are especially prevalent for bandwidth hungry devices, such as, for example, 3D GPU (graphics processor unit) cards, full motion video adapters, Ethernet host bus adapters, FDDI devices, etc. In addition to the speed requirements of the hardware devices, popular software applications prevalent today demand extremely fast updates of graphic and video images (e.g., moving or resizing multiple video windows) without imposing unacceptable system “stuttering” or delays on the end user. Such real-time graphics manipulation requires the updating and moving of large blocks of data (e.g., between system memory, graphics memory, etc.). Hence, an efficient bus architecture is an important element in determining the computer system's overall performance.
PCI Express comprises a high-speed peripheral interconnect architecture first introduced in 2002. PCI Express is intended to eventually replace the earlier developed PCI and AGP bus standards. The objective of PCI Express was to accommodate the higher speeds of the increasingly powerful CPUs, GPUs, and high performance I/O devices (e.g., Gigabit and 10 Gigabit Ethernet, etc.).
PCI Express is based on a high-speed, switched architecture, as opposed to the shared, parallel bus structure of the earlier AGP and PCI standards. Each PCI Express link, or lane, is a serial communications channel made up of two differential signaling wire pairs that provide 2.5 Gb/sec of communications bandwidth in each direction. In a high performance implementation, up to 32 of these “lanes” may be combined in x1, x2, x4, x8, and x16 configurations, creating a parallel interface of independently controlled serial links. The bandwidth of the switch backplane (e.g., the motherboard) is one factor that determines the total capacity of a PCI Express implementation.
The number of PCIe lanes is typically dictated by cost constraints. For example, a 4-layer PCB (printed circuit board) is less expensive than a 6, 8 (or greater number) layer PCB. As such, flexibility considerations in having a large number of PCIe lanes cannot overshadow practical cost considerations. For example, an additional number of PCIe lanes somewhere beyond about 20 starts causing trace routing problems (e.g., not enough space to adequately route the traces) for 4-layer, and potentially 6- and 8-layer motherboards. So having 28 lanes presents a much more difficult trace routing problem, which includes the difficulty in physically “breaking out” of the BGA package, also known as “pin escaping”. Such considerations as cause the industry standard x86 architecture to coalesce around PCIe implementations having 20 lanes.
A problem exist however, in the standardized configuration of the chipset architectures of mass-produced computer systems (e.g., industry standard x86 machines). As described above, the majority of industry standard x86 chipsets are built around a switch backplane supporting a total capacity of 20 PCI Express lanes. The chipsets employ one “x16” PCI Express connector for the bandwidth hungry graphics subsystem (e.g., an add-in PCI Express GPU card), and four “x1” connectors for I/O devices (e.g., Ethernet, etc.). The problem, however, is that there are many emerging applications that greatly benefit from two high bandwidth connections to the computer system as opposed to one x16 connection.
Two high bandwidth connections would allow the use of two high performance, high bandwidth devices. However, the majority of the x86 chipsets do not implement two high bandwidth PCI Express connectors. The trace routing constraints, signal quality constraints, multi-layer PCB manufacturing costs, etc., render the simple addition of an extra x16 PCI Express connector to the motherboard problematic. Additionally, there are a limited number of connectors available on a typical industry standard motherboard (e.g., ATX motherboard, etc.). Thus, a need exists for an efficient way to flexibly accommodate two high bandwidth PCI Express connectors on a motherboard.